1. Field of the Invention
The present invention relates to a method for manufacturing a memory element, and more particularly, to a method for manufacturing a NAND flash memory.
2. Description of the Related Art
Flash memory has become a kind of nonvolatile memory widely used in personal computers (PCs) and electronic products, as it is capable of storing, reading and erasing data for several times, and the data stored therein will be retained even after a power to the device is cut off.
A typical flash memory has a floating gate and a control gate comprised of doped poly-silicon. Generally, the higher the gate-coupling ratio (GCR) between the floating gate and the control gate, the lower the working voltage required, and correspondingly the higher the operation speed of the memory. The GCR refers to the ratio of a capacitance value between the float gate and the control gate to an overall capacitance value of the memory, such that increasing an equivalent capacitor area between the float gate and the control gate will facilitate increase in the GCR.
However, to satisfy design trends for integrated circuits (ICs), continuously pursuing increasingly higher integration, the area occupied by each memory cell must be reduced and the line width of the element must also be reduced. Thus, the GCR between the floating gate and the control gate will be reduced accordingly, and thereby, the working voltage required by nonvolatile memory will be increased. This is quite disadvantageous for nonvolatile memory which is applied in portable electronic products which demand low power consumption.
Referring to FIG. 1, a flash memory disclosed in U.S. Pat. No. 6,897,116 is shown, wherein the flash memory is disposed on a substrate 110 and comprises a gate oxide layer 111, floating gates 130, insulating stacked structures 115, and control gates 116 sequentially arranged thereon. The floating gates 130 with semiconductor spacers are utilized to increase an equivalent capacitor area between the floating gates 130 and the control gates 116. Thus, the GCR of the flash memory can be increased.
However, in the above flash memory, the gaps between the floating gates 130 are relatively small, so that short circuits easily occur in the floating gates 130 due to incomplete etching or conductor scraps dropped in the gaps; and the whole flash memory may be rendered defective.
Besides, the above flash memory is an NOR type array structure with larger area and lower integration. In other words, the capacity of this NOR flash memory is relatively small, and therefore not suitable for products requiring large memory capacity.
As for ordinary NAND flash memory, in order to increase the GCR, the floating gates are usually disposed across the isolation structures to increase the equivalent capacitor area between the floating gates and the control gates. However, since the floating gates are formed through lithographic etching, as the size of elements become increasingly small, overlaying errors easily occur during exposure and development, and thereby causing short circuits in the memory, and the reliability of the memory is deteriorated.
Therefore, how to manufacture a flash memory with a high coupling ratio and high integration in a limited chip area through a simple method is an important issue.